The present invention relates to a nonvolatile semiconductor memory device, in particular, a nonvolatile semiconductor memory device employing a multi-valued write method using channel hot electrons.
Conventionally, as a most commonly used nonvolatile semiconductor memory device, flash memory of an ETOX (EPROM Thin Oxide, a registered trade name of a product of Intel Corporation) type can be mentioned. FIG. 8 is a schematic cross sectional view showing a memory cell of this ETOX-type flash memory. As shown in FIG. 8, a floating gate 64 is formed on a substrate 60 on which a source 61 and a drain 62 are formed with a predetermined gap therebetween and a region between the source 61 and the drain 62 via a tunnel oxide film 63, and a control gate 66 is further formed on the floating gate 64 via an interlayer insulating film 65.
An operation principle of this ETOX-type flash memory is described below. As shown in Table 1 as voltage conditions, at the time of a write operation, a write voltage Vpp (for example, 9 V) is applied to the control gate 66, a standard voltage Vss (for example, 0 V) is applied to the source, and a voltage of 5 V is applied to the drain 62.
It is noted that the drain 62 of a memory cell to which data is not written is opened. Consequently, a large amount of current flows in a channel layer, hot electrons are generated in a portion on the drain side where an electric field is high, electrons are implanted into the floating gate 64, and a threshold voltage of the memory cell is raised. FIG. 9 shows a state of threshold voltages of two-valued flash memories. The right side of FIG. 9 is a distribution state of threshold voltages in a program (written) state with data xe2x80x9c0xe2x80x9d.
Furthermore, at the time of an erase operation, Vnn (for example, xe2x88x929 V) is applied to the control gate 66, Vpe (for example, 6 V) is applied to the source 61, and electrons are pulled from the floating gate 64 on the source side to lower a threshold voltage. The left side of FIG. 9 is a distribution state threshold voltages in an erased state with data xe2x80x9c1xe2x80x9d. Upon this erase operation, a BTBT (Band To Band Tunneling) current flows from the source side to the substrate 60. When this current is generated, hot holes and hot electrons are generated at the same time. Of these, the hot electrons flow to the drain 62, but, on the other hand, the hot holes are pulled to the tunnel oxide film 63 side and trapped inside the tunnel oxide film 63. Generally, this trap is considered to deteriorate reliability.
Furthermore, at the time of a read operation, 1 V is applied to the drain 62, and 5 V is applied to the control gate 66. When a memory cell is in an erased state and the threshold voltage is low, a current flows through the memory cell, and data xe2x80x9c1xe2x80x9d is determined. On the other hand, when a memory cell is in a program state and the threshold voltage is high, a current does not flow through the memory cell, and data xe2x80x9c0xe2x80x9d is determined.
Meanwhile, recently, multi-valued techniques are being developed for the purpose of lower costs. FIGS. 10A to 10D are conceptual diagrams showing a state electrons in a floating gate in the case of a four-valued flash memory using the multi-valued technique (the one shown in FIG. 10 is a four-valued one, while FIG. 11 shows a two-valued one for comparison). As shown in FIG. 10, a state at each level is determined by the number of electrons in the floating gate. The state of the threshold voltage in this case is divided into four threshold voltage levels as shown in FIG. 12 as follows.
Data xe2x80x9c00xe2x80x9d: threshold voltage of 5.7 V or higher
Data xe2x80x9c01xe2x80x9d: threshold voltage of 4.7-5.0 V
Data xe2x80x9c10xe2x80x9d: threshold voltage of 3.7-4 V
Data xe2x80x9c11xe2x80x9d: threshold voltage of 3.0 V or lower
Such a state of the threshold voltage is adjusted by controlling the amount of electrons to be implanted into the floating gate by utilizing a characteristic that the threshold voltage is changed by the number of electrons in the floating gate shown in FIG. 10.
A point of this multi-valued technique is how the threshold voltage (in particular, threshold voltages for data xe2x80x9c01xe2x80x9d and data xe2x80x9c10xe2x80x9d, which are intermediate levels) is made within a predetermined threshold voltage.
Procedures of this multi-valued technique are described below. A general write method is disclosed in Japanese Patent Laid-Open Publication No. 2001-57091 and IEEE J. Solid-State Circuits, Vol. 35, No. 41, pp. 1655-1667, November, 2000, xe2x80x9c40 mm2 3 V Only 50 MHz 64 Mb 2 b/cell CHE NOR Flash Memoryxe2x80x9d. The method described in these references includes procedures in which program (write) pulse application and a verify operation for verifying a threshold voltage of a memory cell after program pulse application are repeated, and the drain of a memory cell of which threshold voltage reaches a predetermined threshold voltage is opened in subsequent program pulse application so that a drain voltage is not applied thereto, while 5 V is applied to the drain of a memory cell of which threshold voltage does not reach the predetermined threshold voltage, and a program pulse is applied to continue a write operation. When threshold voltages of all memory cells to be programmed (written) finally reach the predetermined threshold voltage, the write operation is terminated.
In particular, a procedure is described in which a voltage applied to the control gate is set to be low at the time of a first program (write) operation and the voltage of the control gate is raised by a certain voltage for each program pulse application in order to increase a program (write) speed in this case. FIG. 13 shows a write algorithm in this case.
As shown in FIG. 13, when a program is started, N is set at zero in step S1, and a verify operation is performed in step S2 to determine whether a threshold voltage of a memory cell is 3.7 V or higher. Then, when the threshold voltage of the memory cell is lower than 3.7 V, N is increased by an increment (N+1) in step S3. The operation proceeds to step S4, and a gate voltage Vg (=Vg10) is raised by xcex94Vgxc3x97(Nxe2x88x921). In step S5, a write pulse having a voltage of Vg+xcex94Vgxc3x97(Nxe2x88x921) is applied to the control gate. Then, the operation returns to step S2, and steps S2 to S5 are repeated until the threshold voltage of the memory cell becomes 3.7 V or higher.
On the other hand, when the threshold voltage of the memory cell is 3.7 V or higher in step S2, the operation proceeds to step S11, and N is set at zero. A verify operation is performed in step S12 to determine whether the threshold voltage of the memory cell is 4.7 V or higher. Then, when the threshold voltage of the memory cell is lower than 4.7 V, N is increased by an increment (N+1) in step S13. The operation proceeds to step S14, and the gate voltage Vg (=Vg01) is raised by xcex94Vgxc3x97(Nxe2x88x921). In step S15, a write pulse having a voltage of Vg +xcex94Vgxc3x97(Nxe2x88x921) is applied to the control gate. Then, the operation returns to step S12, and steps S12 to S15 are repeated until the threshold voltage of the memory cell becomes 4.7 V or higher.
On the other hand, when the threshold voltage of the memory cell is 4.7 V or higher in step S12, the operation proceeds to step S21 shown in FIG. 14, and N is set at zero. A verify operation is performed in step S22 to determine whether the threshold voltage of the memory cell is 5.7 V or higher. Then, when the threshold voltage of the memory cell is lower than 5.7 V, N is increased by an increment (N+1) in step S23. The operation proceeds to step S24, and the gate voltage Vg (=Vg00) is raised by xcex94Vgxc3x97(Nxe2x88x921). In step S25, a write pulse having a voltage of Vg +xcex94Vgxc3x97(Nxe2x88x921) is applied to the control gate. Then, the operation returns to step S22, and steps S22 to S25 are repeated until the threshold voltage of the memory cell becomes 5.7 V or higher.
On the other hand, when the threshold voltage of the memory cell is 5.7 V or higher in step S22, this processing is terminated.
In FIG. 13, steps SI to S5 are write processing of data xe2x80x9c10xe2x80x9d, and Vg10 is a start voltage (write start voltage) of data xe2x80x9c10xe2x80x9d at the time of a write operation. Furthermore, steps S11 to S15 are write processing of data xe2x80x9c01xe2x80x9d, and Vg10 is a start voltage of data xe2x80x9c01xe2x80x9d at the time of a write operation. Steps S21 to 525 are write processing of data xe2x80x9c00xe2x80x9d, and Vg00 is a start voltage of data xe2x80x9c00xe2x80x9d at the time of a write operation.
Meanwhile, FIG. 15 shows transition of voltages applied to the control gate in program pulse application.
A write principle of this procedure is described in view of characteristics of a memory cell. First, FIG. 16 shows a distribution of threshold voltages Vt of memory cells when a program pulse is applied once with a gate voltage of Vg10 (for example, 6 V) and a drain voltage of Vd (for example, 5 V). It is shown that the threshold voltages are distributed from 2.7 to 3.7 V. An upper limit of the distribution in this case is 3.7 V (Vtmax), and a lower limit is 2.7 V (Vtmin). Here, after the control gate voltage is set at 6 V and the drain voltage is set at 5 V, for example, a program (write) operation is performed once. A threshold voltage distribution in this case is distribution 1 (corresponding to FIG. 16) shown in FIG. 17. Then, when the control gate voltage is raised successively to 6.5 V and a program (write) operation is performed, the whole threshold voltages shift to distribution 2 shown in FIG. 17. Meanwhile, when the control gate voltage is further increased by 0.5 V to 7 V and a program pulse is applied, the distribution of the threshold voltages of the memory cells becomes as shown as distribution 3. Subsequently, while the control gate voltage is similarly raised and a write operation is performed, the threshold voltage distribution becomes as shown as distribution 4. Relations between the upper limit threshold voltage Vtmax, lower limit threshold voltage Vtmin and control gate voltage at this time are as shown in FIG. 18. This relationship can be converted to relations of the number n of pulses applied when the control gate voltage is raised by each voltage increment xcex94Vg. When the upper limit threshold voltage Vtmax and the lower limit threshold voltage Vtmin at the gate voltage of 6 V upon the first program pulse application to the control gate are assumed as Vtmaxi and Vtmini, respectively, the following relations are satisfied:
Vtmax=Vtmaxi+xcex94Vgxc3x97(nxe2x88x921)
Vtmin=Vtmini+xcex94Vgxc3x97(nxe2x88x921)
(wherein xcex94Vg is Vgxe2x88x926 V, and n is the number of pulses applied). That is, a relationship of xcex94Vt=xcex94Vg is satisfied.
As shown in these expressions, by setting the voltage increment xcex94Vg of a control gate voltage to be 0.3 V in a program algorithm in which the control gate voltage is raised as described above for data xe2x80x9c01xe2x80x9d and data xe2x80x9c10xe2x80x9d, the threshold voltage increment can be limited to 0.3 V or lower. That is, the threshold voltage can be set to be 4.7 to 5 V for data xe2x80x9c01xe2x80x9d, and the threshold voltage can be set to be 3.7 to 4 V for data xe2x80x9c10xe2x80x9d. For example, in order to limit a threshold voltage of a memory cell that stores data xe2x80x9c10xe2x80x9d within a range of 3.7 to 4 V, the control gate voltage is set such that the upper limit threshold voltage Vtmax reaches the range of 3.7 to 4 V. When the control gate voltage in this case is set to be 6 V, the following are obtained:
1st pulse (6 V): Vg Vtmin=2.7 V
2nd pulse (6.3 V): Vg+xcex94Vg Vtmin=3.0 V
3rd pulse (6.6 V): Vg+2xcex94Vg Vtmin=3.3 V
4th pulse (6.9 V): Vg+3xcex94Vg Vtmin=3.6 V
5th pulse (7.2 V): Vg+4xcex94Vg Vtmin=3.9 V
With this 5th pulse (voltage applied to the control gate is 7.2 V), the threshold voltage of even a memory cell with the slowest write speed due to variations in write characteristics of memory cells should become 3.9 V or higher, that is, 3.7 V or higher.
In practice, a verify operation is performed for each program pulse application, and a threshold voltage is determined from a memory cell current that flows in a memory cell by this verify operation (basically the same as a read operation) Since the drain of a memory cell of which threshold voltage reaches 3.7 V or higher is opened, and thereafter a write operation is not performed in this processing, all the write operations of memory cells to which data xe2x80x9c10xe2x80x9d is to be written is terminated with this 5th pulse application.
Thus, since a procedure is used in which a verify operation is performed for each pulse application, and a voltage is not applied to the drain of a memory cell of which threshold voltage reaches 3.7 V or higher, the threshold voltage increment can be limited to 0.3 V or lower.
A threshold voltage of a memory cell that stores data xe2x80x9c01xe2x80x9d can be limited within a range of 4.7 to 5 V with a similar procedure. That is, by applying pulses so that the upper limit threshold voltage Vtmax reaches the range of 4.7 to 5 V, the lower limit threshold voltage Vtmin becomes 4.8 V with an 8th pulse.
Meanwhile, if characteristics of memory cells vary depending on each device in a four-valued flash memory as the nonvolatile semiconductor memory device, as a practical problem, a device in which the above relationship of xcex94Vt=xcex94Vg is not satisfied occurs. At this time, a problem arises in the following cases (1) and (2).
[(1) In the case of xcex94Vt greater than xcex94Vg]
In the case of, for example, xcex94Vt=1.2xc3x97xcex94Vg, when the gate voltage is increased by each voltage increment xcex94Vg=0.3 V, a change of the threshold voltage becomes xcex94Vt=0.36 V, and, as a result, the threshold voltage distribution falls within the range of 3.7 to 4.06 V. Consequently, the threshold voltage distribution varies more than predetermined values, and this expansion of the threshold voltage distribution is expected to lead to a decrease of a margin when the memory cell current is decided upon a read operation, resulting in a defective read operation.
[(2) In the case of xcex94Vt less than xcex94Vg]
In the case of, for example, xcex94Vt=0.8xc3x97xcex94Vg, when the gate voltage is increased by each voltage increment xcex94Vg=0.3 V, the threshold voltage change becomes xcex94Vt=0.24 V. In this case, the threshold voltage distribution is limited within the predetermined range of 3.7 to 4.0 V, but the following is obtained:
1st pulse (6 V): Vg Vtmin=2.7 V
2nd pulse (6.3 V): Vg+xcex94Vg Vtmin=2.94 V
3rd pulse (6.6 V): Vg+2xcex94Vg Vtmin=3.18 V
4th pulse (6.9 V): Vg+3xcex94Vg Vtmin=3.42 V
5th pulse (7.2 V): Vg+4xcex94Vg Vtmin=3.66 V
6th pulse (7.2 V): Vg+5xcex94Vg Vtmin=3.9 V
Thus, the number of required pulses is increased. The increase in the number of pulses further result in an increase in the number of verify operations performed for each pulse application, and a problem arises as a result that a program speed is deteriorated.
Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device with which a multi-valued write operation with high reliability can be performed in which a read margin can be secured without being affected by variations in devices and deteriorating a program speed.
In order to achieve the above object, there is provided an electrically writable and erasable nonvolatile semiconductor memory device composed of one or more chips and having memory cells respectively constituted by a floating gate field effect transistor including a control gate, a drain, a source and a floating gate, wherein charged states corresponding to three or more values are generated in the floating gate, comprising:
write means that, at the time of write operation for generating one of two or more charged states of the floating gate corresponding to two or more values, performs a first step of applying a write pulse being a positive write start voltage to the control gate, and thereafter repeatedly performs a second step of applying a write pulse to the control gate of the transistor of a memory cell which is not judged to be in a predetermined charged state, wherein the write pulse in the second step is repeatedly raised by a voltage increment until the transistor of the memory cell becomes the predetermined charged state, wherein
a voltage increment setting means for setting the voltage increment in the second step for each chip.
According to the nonvolatile semiconductor memory device having the above constitution, a voltage increment by which the change of the threshold voltage of the memory cell falls within a predetermined voltage width can be set for each chip in the write means without being affected by the variations in devices, and a multi-valued write operation with high reliability can be performed in which read margin can be secured without deteriorating a program speed.
In one embodiment of the present invention, the write means includes:
voltage supply means for supplying a voltage to the control gate;
write control means for outputting a write control signal to the voltage supply means; and
storage means for storing information of the voltage increment; and
the voltage supply means successively supplies voltages raised by the voltage increment based on the information of the voltage increment stored in the storage means to the control gate according to a write control signal from the write control means.
According to the nonvolatile semiconductor memory device of the above embodiment, since the voltage supply means supplies a voltage successively increased by the voltage increment to the control gate by a write control signal from the write control means based on voltage increment information stored in the storage means, write pulses can be applied to the control gate by the voltage increment set for each chip with a simple constitution.
In one embodiment of the present invention, the write means includes:
voltage supply means for supplying a voltage to the control gate;
write control means for outputting a write control signal to the voltage supply means; and
storage means for storing a numerical value corresponding to the voltage increment as information of the voltage increment;
the write control means successively adds a numerical value corresponding to the voltage increment stored in the storage means to the positive write start voltage, and outputs a write control signal representing the positive write start voltage and added results; and
the voltage supply means supplies a voltage corresponding to the write control signal from the write control means to the control gate.
According to the nonvolatile semiconductor memory device of the above embodiment, since the write control means outputs a write control signal representing a result obtained by successively adding a numerical value corresponding to a voltage increment stored in the storage means to the numerical value corresponding to the positive write start voltage, and a voltage corresponding to the result represented by the write control signal is supplied from the voltage supply means to the control gate, a write pulse can be applied to the control gate by the voltage increment set for each chip with a simple constitution.
In one embodiment of the present invention, information of the voltage increment by which a change of the threshold voltage of a memory cell obtained by a test of a write characteristic becomes a predetermined voltage is stored in the storage means.
According to the nonvolatile semiconductor memory device of the above embodiment, since information of the voltage increment which is obtained from a test of write characteristics and by which a change in a threshold voltage of a memory cell becomes a predetermined voltage is stored in the storage means, and a voltage is supplied from the voltage supply means to the control gate based on the information stored in the storage means, the change in the threshold voltage of the memory cell can be made within the same predetermined voltage width irrespective of variations in chip characteristics.
In one embodiment of the present invention, a memory cell having the same constitution as the memory cell is used as the storage means.
According to the nonvolatile semiconductor memory device of the above embodiment, since a memory cell having the same constitution as the memory cell is used as the storage means, it is sufficient to use a part of the memory cells constituting a cell array made of the memory cells, for example, and no special storage means needs to be newly designed. Therefore, a chip area can be reduced.
In one embodiment of the present invention, the voltage supply means supplies a voltage generated by a resistive potential divider to the control gate.
According to the nonvolatile semiconductor memory device of the above embodiment, since the voltage supply means supplies a voltage generated by a resistive potential divider made of resistors connected in series to the control gate, a layout area can be reduced with a simplest constitution. Since a resistance ratio is stable even if resistance values vary depending on device (chip) manufacturing conditions, a stable voltage increment can be reliably obtained.